With the imminent introduction of digital television and high definition television (HDTV), the signal processing requirements of digital video delivery systems have recently received much attention. The current trend in the industry is to digitize the analog signal as soon as possible at a low rate and process the signal digitally. Digital signal processing algorithms such as adaptive filtering and equalization are critical for such systems and have long been used in telephone modem applications. However, the bit rate requirement for compressed video data is an order of magnitude greater than that for telephone modems.
For a HDTV system, the symbol rate at the receiver is approximately 6 MHz. An adaptive equalizer, used to reduce the intersymbol interference of the incoming signal, requires approximately a 100-tap filter for the equalizer. Even when using the simplest Least Mean Square (LMS) algorithm for updating the filter coefficients at every sample, the computational requirements are beyond the capabilities of any programmable digital signal processor in the market today. The complexity of the LMS algorithm is known to be 3N where N is number of taps. Therefore, if the coefficients of the equalizer is to be updated at every sample, the required processing power would be approximately 3N*6.0.times.10.sup.6, i.e., 1,800 Million for N=100, instructions per second.
The conventional approach to resolve this problem is to assume that the channel characteristics are changing much slower than the symbol rate. This assumption permits filter coefficient updates at a much slower rate. The resulting system architecture consists of dedicated hardware for the filter section and a programmable digital signal processor (DSP) for error computation and new coefficient generation. Current application specific integrated circuit (ASIC) technology enables us to develop dedicated filter chips for the equalizer which can operate at high input sample rates. However, depending on the application, a conventional custom chip cannot provide an adequate level of performance when both a wide input data width, e.g. greater than 16 bits and high sample rates are required.
To overcome this limitation, various approaches have been proposed to parallelize the equalizer structure. Previously, parallelization of the decision feedback equalizer has been developed based on block updates using an extended LMS algorithm for filter update. In this scheme, the input data samples are broken into multiple blocks with the same number of samples each. They are then processed by multiple decision feedback equalizers in parallel. Also, another parallel scheme uses a double-row decision feedback equalizer algorithm. These schemes have the disadvantage of requiring more hardware and are not suited to applications where fast coefficient updates are required.
Accordingly, a need has arisen for a decision feedback equalizer which can accommodate a wide input data width and high sampling rates, and does not involve more complex hardware.